ARTIFICIAL INTELLIGENCE HARDWARE DESIGN
Learn foundational and advanced topics in Neural Processing Unit design with real-world examples from leading voices in the field
In Artificial Intelligence Hardware Design: Challenges and Solutions, distinguished researchers and authors Drs. Albert Chun Chen Liu and Oscar Ming Kin Law deliver a rigorous and practical treatment of the design applications of specific circuits and systems for accelerating neural network processing. Beginning with a discussion and explanation of neural networks and their developmental history, the book goes on to describe parallel architectures, streaming graphs for massive parallel computation, and convolution optimization.
The authors offer readers an illustration of in-memory computation through Georgia Tech's Neurocube and Stanford's Tetris accelerator using the Hybrid Memory Cube, as well as near-memory architecture through the embedded eDRAM of the Institute of Computing Technology, the Chinese Academy of Science, and other institutions.
Readers will also find a discussion of 3D neural processing techniques to support multiple layer neural networks, as well as information like:
* A thorough introduction to neural networks and neural network development history, as well as Convolutional Neural Network (CNN) models
* Explorations of various parallel architectures, including the Intel CPU, Nvidia GPU, Google TPU, and Microsoft NPU, emphasizing hardware and software integration for performance improvement
* Discussions of streaming graph for massive parallel computation with the Blaize GSP and Graphcore IPU
* An examination of how to optimize convolution with UCLA Deep Convolutional Neural Network accelerator filter decomposition
Perfect for hardware and software engineers and firmware developers, Artificial Intelligence Hardware Design is an indispensable resource for anyone working with Neural Processing Units in either a hardware or software capacity.
Autorentext
Albert Chun Chen Liu, PhD, is Chief Executive Officer of Kneron. He is Adjunct Associate Professor at National Tsing Hua University, National Chiao Tung University, and National Cheng Kung University. He has published over 15 IEEE papers and is an IEEE Senior Member. He is a recipient of the IBM Problem Solving Award based on the use of the EIP tool suite in 2007 and IEEE TCAS Darlington award in 2021.
Oscar Ming Kin Law, PhD, is the Director of Engineering at Kneron. He works on smart robot development and in-memory architecture for neural networks. He has over twenty years of experience in the semiconductor industry working with CPU, GPU, and mobile design. He has also published over 60 patents in various areas.
Klappentext
Learn foundational and advanced topics in Neural Processing Unit design with real-world examples from leading voices in the field
In Artificial Intelligence Hardware Design: Challenges and Solutions, distinguished researchers and authors Drs. Albert Chun Chen Liu and Oscar Ming Kin Law deliver a rigorous and practical treatment of the design applications of specific circuits and systems for accelerating neural network processing. Beginning with a discussion and explanation of neural networks and their developmental history, the book goes on to describe parallel architectures, streaming graphs for massive parallel computation, and convolution optimization.
The authors offer readers an illustration of in-memory computation through Georgia Tech's Neurocube and Stanford's Tetris accelerator using the Hybrid Memory Cube, as well as near-memory architecture through the embedded eDRAM of the Institute of Computing Technology, the Chinese Academy of Science, and other institutions.
Readers will also find a discussion of 3D neural processing techniques to support multiple layer neural networks, as well as information like:
- A thorough introduction to neural networks and neural network development history, as well as Convolutional Neural Network (CNN) models
- Explorations of various parallel architectures, including the Intel CPU, Nvidia GPU, Google TPU, and Microsoft NPU, emphasizing hardware and software integration for performance improvement
- Discussions of streaming graph for massive parallel computation with the Blaize GSP and Graphcore IPU
- An examination of how to optimize convolution with UCLA Deep Convolutional Neural Network accelerator filter decomposition
Perfect for hardware and software engineers and firmware developers, Artificial Intelligence Hardware Design is an indispensable resource for anyone working with Neural Processing Units in either a hardware or software capacity.
Zusammenfassung
ARTIFICIAL INTELLIGENCE HARDWARE DESIGN
Learn foundational and advanced topics in Neural Processing Unit design with real-world examples from leading voices in the field
In Artificial Intelligence Hardware Design: Challenges and Solutions, distinguished researchers and authors Drs. Albert Chun Chen Liu and Oscar Ming Kin Law deliver a rigorous and practical treatment of the design applications of specific circuits and systems for accelerating neural network processing. Beginning with a discussion and explanation of neural networks and their developmental history, the book goes on to describe parallel architectures, streaming graphs for massive parallel computation, and convolution optimization.
The authors offer readers an illustration of in-memory computation through Georgia Tech's Neurocube and Stanford's Tetris accelerator using the Hybrid Memory Cube, as well as near-memory architecture through the embedded eDRAM of the Institute of Computing Technology, the Chinese Academy of Science, and other institutions.
Readers will also find a discussion of 3D neural processing techniques to support multiple layer neural networks, as well as information like:
- A thorough introduction to neural networks and neural network development history, as well as Convolutional Neural Network (CNN) models
- Explorations of various parallel architectures, including the Intel CPU, Nvidia GPU, Google TPU, and Microsoft NPU, emphasizing hardware and software integration for performance improvement
- Discussions of streaming graph for massive parallel computation with the Blaize GSP and Graphcore IPU
- An examination of how to optimize convolution with UCLA Deep Convolutional Neural Network accelerator filter decomposition
Perfect for hardware and software engineers and firmware developers, Artificial Intelligence Hardware Design is an indispensable resource for anyone working with Neural Processing Units in either a hardware or software capacity.
Inhalt
Author Biographies xi
Preface xiii
Acknowledgments xv
Table of Figures xvii
1 Introduction 1
1.1 Development History 2
1.2 Neural Network Models 4
1.3 Neural Network Classification 4
1.3.1 Supervised Learning 4
1.3.2 Semi-supervised Learning 5
1.3.3 Unsupervised Learning 6
1.4 Neural Network Framework 6
1.5 Neural Network Comparison 10
Exercise 11
References 12
2 Deep Learning 13
2.1 Neural Network Layer 13
2.1.1 Convolutional Layer 13
2.1.2 Activation Layer 17
2.1.3 Pooling Layer 18
2.1.4 Normalization Layer 19
2.1.5 Dropout Layer 20
2.1.6 Fully Connected Layer 20
2.2 Deep Learning Challenges 22
Exercise 22
References 24
3 Parallel Architecture 25
3.1 Intel Central Processing Unit (CPU) 25
3.1.1 Skylake Mesh Architecture 27
3.1.2 Intel Ultra Path Interconnect (UPI) 28
3.1.3 Sub Non-unified …