Making VHDL a simple and easy-to-use hardware description
language

Many engineers encountering VHDL (very high speed integrated
circuits hardware description language) for the first time can feel
overwhelmed by it. This book bridges the gap between the VHDL
language and the hardware that results from logic synthesis with
clear organisation, progressing from the basics of combinational
logic, types, and operators; through special structures such as
tristate buses, register banks and memories, to advanced themes
such as developing your own packages, writing test benches and
using the full range of synthesis types.

This third edition has been substantially rewritten to include
the new VHDL-2008 features that enable synthesis of fixed-point and
floating-point hardware. Extensively updated throughout to reflect
modern logic synthesis usage, it also contains a complete case
study to demonstrate the updated features.

Features to this edition include:

* a common VHDL subset which will work across a range of
different synthesis systems, targeting a very wide range of
technologies

* a design style that results in long design lifetimes, maximum
design reuse and easy technology retargeting

* a new chapter on a large scale design example based on a
digital filter from design objective and design process, to testing
strategy and test benches

* a chapter on writing test benches, with everything needed to
implement a test-based design strategy

* extensive coverage of data path design, including integer,
fixed-point and floating-point arithmetic, logic circuits,
shifters, tristate buses, RAMs, ROMs, state machines, and
decoders

Focused specifically on logic synthesis, this book is for
professional hardware engineers using VHDL for logic synthesis, and
digital systems designers new to VHDL but familiar with digital
systems. It offers all the knowledge and tools needed to use VHDL
for logic synthesis. Organised in themed chapters and with a
comprehensive index, this complete reference will also benefit
postgraduate students following courses on microelectronics or
VLSI/ semiconductors and digital design.

Andrew Rushton, TransEDA Ltd., Southampton, UK
Dr Rushton previously worked as an industrial hardware engineer at TransEDA Ltd., the leader in Verification Closure Measurement solutions for electronic designs. He now runs his own website design and programming consultancy company, www.andyrushton.co.uk.

Many engineers encountering VHDL (very high speed integrated circuits hardware description language) for the first time can feel overwhelmed by it. This book bridges the gap between the VHDL language and the hardware that results from logic synthesis with clear organisation, progressing from the basics of combinational logic, types, and operators; through special structures such as tristate buses, register banks and memories, to advanced themes such as developing your own packages, writing test benches and using the full range of synthesis types.

This third edition has been substantially rewritten to include the new VHDL-2008 features that enable synthesis of fixed-point and floating-point hardware. Extensively updated throughout to reflect modern logic synthesis usage, it also contains a complete case study to demonstrate the updated features.

Features to this edition include:

• a common VHDL subset which will work across a range of different synthesis systems, targeting a very wide range of technologies
• a design style that results in long design lifetimes, maximum design reuse and easy technology retargeting
• a new chapter on a large scale design example based on a digital filter from design objective and design process, to testing strategy and test benches
• a chapter on writing test benches, with everything needed to implement a test-based design strategy
• extensive coverage of data path design, including integer, fixed-point and floating-point arithmetic, logic circuits, shifters, tristate buses, RAMs, ROMs, state machines, and decoders

Focused specifically on logic synthesis, this book is for professional hardware engineers using VHDL for logic synthesis, and digital systems designers new to VHDL but familiar with digital systems. It offers all the knowledge and tools needed to use VHDL for logic synthesis. Organised in themed chapters and with a comprehensive index, this complete reference will also benefit postgraduate students following courses on microelectronics or VLSI/ semiconductors and digital design.

Preface xi

List of Figures xv

List of Tables xvii

1 Introduction 1

1.1 The VHDL Design Cycle 1

1.2 The Origins of VHDL 2

1.3 The Standardisation Process 3

1.4 Unification of VHDL Standards 4

1.5 Portability 4

2 Register-Transfer Level Design 7

2.1 The RTL Design Stages 8

2.2 Example Circuit 8

2.3 Identify the Data Operations 10

2.4 Determine the Data Precision 12

2.5 Choose Resources to Provide 12

2.6 Allocate Operations to Resources 13

2.7 Design the Controller 14

2.8 Design the Reset Mechanism 15

2.9 VHDL Description of the RTL Design 15

2.10 Synthesis Results 16

3 Combinational Logic 19

3.1 Design Units 19

3.2 Entities and Architectures 20

3.3 Simulation Model 22

3.4 Synthesis Templates 25

3.5 Signals and Ports 27

3.6 Initial Values 29

3.7 Simple Signal Assignments 30

3.8 Conditional Signal Assignments 31

3.9 Selected Signal Assignment 33

3.10 Worked Example 34

4 Basic Types 37

4.1 Synthesisable Types 37

4.2 Standard Types 37

4.3 Standard Operators 38

4.4 Type Bit 39

4.5 Type Boolean 39

4.6 Integer Types 41

4.7 Enumeration Types 46

4.8 Multi-Valued Logic Types 47

4.9 Records 48

4.10 Arrays 49

4.11 Aggregates, Strings and Bit-Strings 53

4.12 Attributes 56

4.13 More on Selected Signal Assignments 60

5 Operators 63

5.1 The Standard Operators 63

5.2 Operator Precedence 64

5.3 Boolean Operators 70

5.4 Comparison Operators 73

5.5 Shifting Operators 76

5.6 Arithmetic Operators 79

5.7 Concatenation Operator 84

6 Synthesis Types 85

6.1 Synthesis Type System 85

6.2 Making the Packages Visible 87

6.3 Logic Types - Std_Logic_1164 90

6.4 Numeric Types - Numeric_Std 95

6.5 Fixed-Point Types - Fixed_Pkg 105

6.6 Floating-Point Types - Float_Pkg 119

6.7 Type Conversions 134

6.8 Constant Values 144

6.9 Mixing Types in Expressions 146

6.10 Top-Level Interface 147

7 Std_Logic_Arith 151

7.1 The Std_Logic_Arith Package 151

7.2 Contents of Std_Logic_Arith 152

7.3 Type Conversions 161

7.4 Constant Values 162

7.5 Mixing Types in Expressions 164

8 Sequential VHDL 167

8.1 Processes 167

8.2 Signal Assignments 170

8.3 Variables 171

8.4 If Statements 172

8.5 Case Statements 177

8.6 Latch Inference 178

8.7 Loops 181

8.8 Worked Example 187

9 Registers 191

9.1 Basic D-Type Register 191

9.2 Simulation Model 192

9.3 Synthesis Model 193

9.4 Register Templates 195

9.5 Register Types 199

9.6 Clock Types 199

9.7 Clock Gating 200

9.8 Data Gating 201

9.9 Asynchronous Reset 203

9.10 Synchronous Re…