An effective and cost efficient protection of electronic system against ESD stress pulses specified by IEC 61000-4-2 is paramount for any system design. This pioneering book presents the collective knowledge of system designers and system testing experts and state-of-the-art techniques for achieving efficient system-level ESD protection, with minimum impact on the system performance. All categories of system failures ranging from 'hard' to 'soft' types are considered to review simulation and tool applications that can be used.

The principal focus of System Level ESD Co-Design is defining and establishing the importance of co-design efforts from both IC supplier and system builder perspectives. ESD designers often face challenges in meeting customers' system-level ESD requirements and, therefore, a clear understanding of the techniques presented here will facilitate effective simulation approaches leading to better solutions without compromising system performance.

With contributions from Robert Ashton, Jeffrey Dunnihoo, Micheal Hopkins, Pratik Maheshwari, David Pomerenke, Wolfgang Reinprecht, and Matti Usumaki, readers benefit from hands-on experience and in-depth knowledge in topics ranging from ESD design and the physics of system ESD phenomena to tools and techniques to address soft failures and strategies to design ESD-robust systems that include mobile and automotive applications.

The first dedicated resource to system-level ESD co-design, this is an essential reference for industry ESD designers, system builders, IC suppliers and customers and also Original Equipment Manufacturers (OEMs).

Key features:

* Clarifies the concept of system level ESD protection.

* Introduces a co-design approach for ESD robust systems.

* Details soft and hard ESD fail mechanisms.

* Detailed protection strategies for both mobile and automotive applications.

* Explains simulation tools and methodology for system level ESD co-design and overviews available test methods and standards.

* Highlights economic benefits of system ESD co-design.

Charvaka Duvvury, formerly Texas Instruments, USA Charvaka Duvvury, formerly of Texas Instruments, is currently working as a technical consultant on ESD design methods and ESD qualification support. He has published over 150 technical papers and holds more than 70 patents. He is a co-founder and co-chair of the Industry Council on ESD Target Levels and has been serving as Board of Director of the ESDA since 1997 promoting university education and research in ESD technology. Harald Gossner, Intel, Germany Harald Gossner is Senior Principal Engineer at Intel where for 15 years he has worked on the development of ESD protection concepts with Siemens and Infineon Technologies. In 2010 he has joined Intel Mobile Communications overseeing the development of robust mobile systems. Harald has authored and co-authored more than 100 technical papers and one book in the field of ESD and device physics. He holds more than 60 patents on the same topic. In 2006 he became cofounder and co-chair of the Industry Council on ESD Target Levels.

List of Contributors xiii

Preface xv

Acronyms xvii

About the Book xxi

1 Introduction 1
Charvaka Duvvury

1.1 Definition of Co-Design 1

1.2 Overview of the Book 2

1.3 Challenges of System Level ESD Protection 2

1.4 Importance of System Level Protection 2

1.5 Industry-Wide Perception 5

1.6 Purpose and Motivation 8

1.7 Organization and Approach 8

1.8 Outcome for the Reader 12

Acknowledgments 12

References 12

2 Component versus System Level ESD 14
Charvaka Duvvury and Harald Gossner

2.1 ESD Threat in the Real World 14

2.1.1 ESD Control 14

2.1.2 ESD Failure Types 15

2.1.3 ESD Protection Areas 16

2.1.4 ESD Stress Models 17

2.2 Component ESD Qualification 17

2.2.1 Component ESD Tests 17

2.2.2 ESD Levels for IC Production 18

2.2.3 Implications for System Level ESD 20

2.2.4 ESD Technology Roadmap 20

2.3 System Level ESD Tests 21

2.3.1 IEC 61000-4-2 22

2.4 ISO 10605 29

2.5 IEC 61000-4-5 31

2.5.1 System Applications 32

2.5.2 Misconceptions and Miscorrelation of Component and System Level Tests 35

2.5.3 Hard Failures Due to IEC Testing 42

2.6 Soft Failures Due to IEC Testing 42

Acknowledgments 43

References 43

3 System Level Testing for ESD Susceptibility 46
Michael Hopkins

3.1 Introduction 46

3.2 Objectives of System Level Testing 47

3.3 Compliance to ESD Standards 47

3.3.1 Legal Compliance Requirements 47

3.3.2 Compliance to Industry Requirements 48

3.4 Testing for Product Reliability 48

3.5 Standards Requirements for System Level Testing 49

3.5.1 IEC 61000-4-2 49

3.5.2 Automotive Standards for ESD 58

3.5.3 Medical Standards for ESD 60

3.5.4 Avionics Standards for ESD 61

3.5.5 Military ESD Standards 61

3.6 Using the IEC Simulator for Device Testing 62

3.7 Cable Discharge (CDE) Testing 63

3.7.1 Shielded Cables 65

3.7.2 Unshielded Cables 65

3.7.3 Modified Transmission Line Pulsers (TLP) for CDE Testing 66

3.8 Evaluation of Test Results 67

3.8.1 Hard Failure Evaluation 67

3.8.2 Soft Failure Evaluation 67

3.9 The Quick Fix vs Root Cause Determination 67

3.10 Determining Root Cause of System Level ESD 68

3.11 Reproducibility of System Level ESD Tests 70

Acknowledgments 72

References 72

4 PCB/IC Co-Design Concepts for SEED 74
Harald Gossner and Charvaka Duvvury

4.1 On-Chip System ESD Protection 74

4.1.1 HBM and CDM vs IEC 74

4.1.2 TLP Characterization 76

4.1.3 TLP Correlation Issues 78

4.2 Off-Chip ESD Protection 79

4.3 Concept of PCB/IC Co-Design 82

4.3.1 On-Chip IEC Protection Solutions 84

4.4 Introduction to System Efficient ESD Design 84

4.4.1 Design Methods for SEED 90

4.4.2 Basic Simulations using SEED 91

4.4.3 USB Design using SEED 94

4.5 Characterization for Hard Failures 97

4.6 Simulation of System Level ESD Discharge Paths 98

4.6.1 Simulation Approach 98

4.6.2 Tools 101

4.6.3 ESD Model Types 103

4.6.4 Extraction of PCB Paths 104

4.6.5 Models of PCB Devices 104

4.6.6 Characterization of IO Cells 106

4.6.7 Power Clamp Models 112

4.6.8 Model for Stress Waveform 114

4.7 Characterization of Soft Failures 116

4.7.1 Purpose and Basic Concept 116

4.7.2 Pin Specific Soft Failure Characterization 120

4.7.3 Soft Failures Related to Signal Integrity Problems 123

4.8 Summary of SEED Characterization 125

Acknowledgments 126

References 127

5 Hard Failures and PCB Protection Devices 129
Robert Ashton

5.1 Introduction 129

5.2 ESD Damage to ICs 129

5.3 Protection Methods 130

5.3.1 Classification of TVS Devices 133

5.4 Characteristics of Protection Devices 134

5.4.1 Current Limiting Devices 134

5.4.2 TVS Properties in Their Off-State 135

5.4.3 Protection Properties of TVS Devices 137

5.5 Types of Protection Devices for ESD 142

5.5.1 Silicon Based TVS Devices 143

5.5.2 Metal Oxide Varistors 154

5.5.3 Polymer Voltage Suppressors 155

5.5.4 Gas Discharge Tubes 156

5.5.5 Spark Gaps on PCBs 158

5.5.6 Thyristor Surge Protection Devices 159

5.5.7 Ferrite Beads 159

5.5.8 Passive Components 161

5.5.9 Common Mode Filters 162

5.6 Primary and Secondary Pro…