Comprehensive coverage of all aspects of space application oriented fault tolerance techniques Experienced expert author working on fault tolerance for Chinese space program for almost three decades Initiatively provides a systematic texts for the cutting-edge fault tolerance techniques in spacecraft control computer, with emphasis on practical engineering knowledge Presents fundamental and advanced theories and technologies in a logical and easy-to-understand manner Beneficial to readers inside and outside the area of space applications
Autorentext
Dr. Yang Mengfei, Professor, Chief Engineer and Chief Commander of China Academy of Space Technology, Beijing, China. Professor Yang Mengfei received his Master's degree in computer application from Beijing Institute of Control Engineering, China Academy of Space Technology in 1985. He then devoted himself to the research of fault tolerance computing, control of computer technology for space applications, and high-dependable software. In 2005, he received Ph.D. degree from Tsinghua University. Professor Yang has received numerous awards for his outstanding work and contribution to this sector.
Dr. Hua Gengxin, Professor, Chief Engineer, Beijing Institute of Control Engineering, Beijing, China.
Dr. Feng Yanjun, Senior Engineer, Director, China Academy of Space Technology, Beijing, China.
Dr. Gong Jian, Senior Engineer, Engineer in Charge, Beijing Institute of Control Engineering, Beijing, China.
Inhalt
Brief Introduction xiii
Preface xv
1 Introduction 1
1.1 Fundamental Concepts and Principles of Fault?-tolerance Techniques 1
1.1.1 Fundamental Concepts 1
1.1.2 Reliability Principles 4
1.1.2.1 Reliability Metrics 4
1.1.2.2 Reliability Model 6
1.2 The Space Environment and Its Hazards for the Spacecraft Control Computer 9
1.2.1 Introduction to Space Environment 9
1.2.1.1 Solar Radiation 9
1.2.1.2 Galactic Cosmic Rays (GCRs) 10
1.2.1.3 Van Allen Radiation Belt 10
1.2.1.4 Secondary Radiation 12
1.2.1.5 Space Surface Charging and Internal Charging 12
1.2.1.6 Summary of Radiation Environment 13
1.2.1.7 Other Space Environments 14
1.2.2 Analysis of Damage Caused by the Space Environment 14
1.2.2.1 Total Ionization Dose (TID) 14
1.2.2.2 Single Event Effect (SEE) 15
1.2.2.3 Internal/surface Charging Damage Effect 20
1.2.2.4 Displacement Damage Effect 20
1.2.2.5 Other Damage Effect 20
1.3 Development Status and Prospects of Fault Tolerance Techniques 21
References 25
2 Fault?-Tolerance Architectures and Key Techniques 29
2.1 Fault?- tolerance Architecture 29
2.1.1 Module?-level Redundancy Structures 30
2.1.2 Backup Fault?-tolerance Structures 32
2.1.2.1 Cold?-backup Fault?-tolerance Structures 32
2.1.2.2 Hot?-backup Fault?-tolerance Structures 34
2.1.3 Triple?-modular Redundancy (TMR) Fault?-tolerance Structures 36
2.1.4 Other Fault?-tolerance Structures 40
2.2 Synchronization Techniques 40
2.2.1 Clock Synchronization System 40
2.2.1.1 Basic Concepts and Fault Modes of the Clock Synchronization System 40
2.2.1.2 Clock Synchronization Algorithm 41
2.2.2 System Synchronization Method 52
2.2.2.1 The Real?-time Multi?-computer System Synchronization Method 52
2.2.2.2 System Synchronization Method with Interruption 56
2.3 Fault?-tolerance Design with Hardware Redundancy 60
2.3.1 Universal Logic Model and Flow in Redundancy Design 60
2.3.2 Scheme Argumentation of Redundancy 61
2.3.2.1 Determination of Redundancy Scheme 61
2.3.2.2 Rules Obeyed in the Scheme Argumentation of Redundancy 62
2.3.3 Redundancy Design and Implementation 63
2.3.3.1 Basic Requirements 63
2.3.3.2 FDMU Design 63
2.3.3.3 CSSU Design 64
2.3.3.4 IPU Design 65
2.3.3.5 Power Supply Isolation Protection 67
2.3.3.6 Testability Design 68
2.3.3.7 Others 68
2.3.4 Validation of Redundancy by Analysis 69
2.3.4.1 Hardware FMEA 69
2.3.4.2 Redundancy Switching Analysis (RSA) 69
2.3.4.3 Analysis of the Common Cause of Failure 69
2.3.4.4 Reliability Analysis and Checking of the Redundancy Power 70
2.3.4.5 Analysis of the Sneak Circuit in the Redundancy Management Circuit 72
2.3.5 Validation of Redundancy by Testing 73
2.3.5.1 Testing by Failure Injection 73
2.3.5.2 Specific Test for the Power of the Redundancy Circuit 74
2.3.5.3 Other Things to Note 74
References 74
3 Fault Detection Techniques 77
3.1 Fault Model 77
3.1.1 Fault Model Classified by Time 78
3.1.2 Fault Model Classified by Space 78
3.2 Fault Detection Techniques 80
3.2.1 Introduction 80
3.2.2 Fault Detection Methods for CPUs 81
3.2.2.1 Fault Detection Methods Used for CPUs 82
3.2.2.2 Example of CPU Fault Detection 83
3.2.3 Fault Detection Methods for Memory 87
3.2.3.1 Fault Detection Method for ROM 88
3.2.3.2 Fault Detection Methods for RAM 91
3.2.4 Fault Detection Methods for I/Os 95
References 96
4 Bus Techniques 99
4.1 Introduction to Space?-borne Bus 99
4.1.1 Fundamental Concepts 99
4.1.2 Fundamental Ter...