The next generation of computer system designers will be less concerned about details of processors and memories, and more concerned about the elements of a system tailored to particular applications. These designers will have a fundamental knowledge of processors and other elements in the system, but the success of their design will depend on the skills in making system-level tradeoffs that optimize the cost, performance and other attributes to meet application requirements. This book provides a new treatment of computer system design, particularly for System-on-Chip (SOC), which addresses the issues mentioned above. It begins with a global introduction, from the high-level view to the lowest common denominator (the chip itself), then moves on to the three main building blocks of an SOC (processor, memory, and interconnect). Next is an overview of what makes SOC unique (its customization ability and the applications that drive it). The final chapter presents future challenges for system design and SOC possibilities.

Michael J. Flynn, Emeritus Professor of Electrical
Engineering at Stanford University, is Chairman of the Board and
Senior Advisor to Maxeler Technologies. Previously, he worked at
IBM in the areas of computer organization and design. His
best-known technical work includes the SIMD/MIMD classification of
computer organization, and the first detailed discussion of
superscalar design. Professor Flynn is a Fellow of the IEEE and a
Fellow of the ACM.

Wayne Luk is Professor of Computer Engineering in the
Department of Computing at Imperial College London, where he
teaches computer architecture and custom computing. He leads the
Computer Systems Section as well as the Custom Computing Research
Group, which is currently focusing on theory and practice of
reconfigurable systems and their design automation. He has worked
with many companies including Altera, J.P. Morgan, Nokia, Sharp,
Sony, and Xilinx. Professor Luk is a Fellow of the IEEE and a
Fellow of the BCS.

As computer systems continue to evolve, the next generation of designers will need to focus less on processors and memories and more on the elements of a system tailored to particular applications. They must understand how to make system-level tradeoffs that optimize cost, performance, and other attributes in order to meet application requirements. To address these needs, this text presents a new, hardware-oriented approach to computer system design, particularly for System-on-Chip (SOC).

Written by leading researchers in computer engineering, the book provides the fundamentals necessary to develop SOC solutions as well as analytical techniques that are relevant to a wide range of architectures and applications. Taking a high-level systems-centric view, it addresses issues that define the design space and describes in detail the three basic elements of SOCprocessor, memory, and interconnect.

To broaden SOC applicability while reducing cost, one can adopt a common hardware platform that can be customized to improve efficiency for specific applications. This book covers different customization technologies for SOC, particularly those based on configurability; it also reveals when customizing is not advisable. Various applications that illustrate the opportunities and system-level trade-offs in SOC design are described, along with explanations of how some of the techniques described in earlier chapters can be applied. Finally, future challenges for system design and SOC possibilities are explored, including autonomous system on a chip and self-optimization and self-verification before and after design deployment.

Complete with problem sets at the end of each chapter as well as a companion website, Computer System Design: System-on-Chip is written for graduate students in computer science, computer engineering, and electrical engineering, as well as for system design professionals, SOC engineers, and computer scientists.

List of Abbreviations and Acronyms xvii

1 Introduction to the Systems Approach 1

1.1 System Architecture: An Overview 1

1.2 Components of the System: Processors, Memories, and Interconnects 2

1.3 Hardware and Software: Programmability Versus Performance 5

1.4 Processor Architectures 7

1.4.1 Processor: A Functional View 8

1.4.2 Processor: An Architectural View 9

1.5 Memory and Addressing 19

1.5.1 SOC Memory Examples 20

1.5.2 Addressing: The Architecture of Memory 21

1.5.3 Memory for SOC Operating System 22

1.6 System-Level Interconnection 24

1.6.1 Bus-Based Approach 24

1.6.2 Network-on-Chip Approach 25

1.7 An Approach for SOC Design 26

1.7.1 Requirements and Specifi cations 26

1.7.2 Design Iteration 27

1.8 System Architecture and Complexity 29

1.9 Product Economics and Implications for SOC 31

1.9.1 Factors Affecting Product Costs 31

1.9.2 Modeling Product Economics and Technology Complexity: The Lesson for SOC 33

1.10 Dealing with Design Complexity 34

1.10.1 Buying IP 34

1.10.2 Reconfi guration 35

1.11 Conclusions 37

1.12 Problem Set 38

2 Chip Basics: Time, Area, Power, Reliability, and Confi gurability 39

2.1 Introduction 39

2.1.1 Design Trade-Offs 39

2.1.2 Requirements and Specifi cations 42

2.2 Cycle Time 43

2.2.1 Defi ning a Cycle 43

2.2.2 Optimum Pipeline 44

2.2.3 Performance 46

2.3 Die Area and Cost 47

2.3.1 Processor Area 47

2.3.2 Processor Subunits 50

2.4 Ideal and Practical Scaling 53

2.5 Power 57

2.6 AreaTimePower Trade-Offs in Processor Design 60

2.6.1 Workstation Processor 60

2.6.2 Embedded Processor 61

2.7 Reliability 62

2.7.1 Dealing with Physical Faults 62

2.7.2 Error Detection and Correction 65

2.7.3 Dealing with Manufacturing Faults 68

2.7.4 Memory and Function Scrubbing 69

2.8 Confi gurability 69

2.8.1 Why Reconfi gurable Design? 69

2.8.2 Area Estimate of Reconfi gurable Devices 70

2.9 Conclusion 71

2.10 Problem Set 71

3 Processors 74

3.1 Introduction 74

3.2 Processor Selection for SOC 76

3.2.1 Overview 76

3.2.2 Example: Soft Processors 76

3.2.3 Examples: Processor Core Selection 79

3.3 Basic Concepts in Processor Architecture 81

3.3.1 Instruction Set 81

3.3.2 Some Instruction Set Conventions 82

3.3.3 Branches 82

3.3.4 Interrupts and Exceptions 84

3.4 Basic Concepts in Processor Microarchitecture 86

3.5 Basic Elements in Instruction Handling 88

3.5.1 The Instruction Decoder and Interlocks 88

3.5.2 Bypassing 90

3.5.3 Execution Unit 90

3.6 Buffers: Minimizing Pipeline Delays 91

3.6.1 Mean Request Rate Buffers 91

3.6.2 Buffers Designed for a Fixed or Maximum Request Rate 92

3.7 Branches: Reducing the Cost of Branches 93

3.7.1 Branch Target Capture: Branch Target Buffers (BTBs) 94

3.7.2 Branch Prediction 97

3.8 More Robust Processors: Vector, Very Long Instruction Word (VLIW), and Superscalar 101

3.9 Vector Processors and Vector Instruction Extensions 101

3.9.1 Vector Functional Units 103

3.10 VLIW Processors 107

3.11 Superscalar Processors 108

3.11.1 Data Dependencies 109

3.11.2 Detecting Instruction Concurrency 110

3.11.3 A Simple Implementation 112

3.11.4 Preserving State with Out-of-Order Execution 116

3.12 Processor Evolution and …