Memory Architecture Exploration for Programmable Embedded Systems addresses efficient exploration of alternative memory architectures, assisted by a "compiler-in-the-loop" that allows effective matching of the target application to the processor-memory architecture. This new approach for memory architecture exploration replaces the traditional black-box view of the memory system and allows for aggressive co-optimization of the programmable processor together with a customized memory system.
The book concludes with a set of experiments demonstrating the utility of this exploration approach. The authors perform architecture and compiler exploration for a set of large, real-life benchmarks, uncovering promising memory configurations from different perspectives, such as cost, performance and power.

List of Figures. List of Tables. Preface. Acknowledgements. 1: Introduction. 1.1. Motivation. 1.2. Memory Architecture Exploration for Embedded Systems. 1.3. Book Organization. 2: Related Work. 2.1.High-Level Synthesis. 2.2. Cache Optimizations. 2.3. Computer Architecture. 2.4. Disk File Systems. 2.5. Heterogeneous Memory Architectures. 2.6. Summary. 3. Early Memory Size Estimation. 3.1. Motivation. 3.2. Memory Estimation Problem. 3.3. Memory Size Estimation Algorithm. 3.4. Discussion on Parallelism vs. Memory Size. 3.5. Experiments. 3.6. Related Work. 3.7. Summary. 4: Early Memory and Connectivity Architecture Exploration. 4.1 Motivation. 4.2. Access Pattern Based Memory Architecture Exploration. 4.3. Connectivity Architecture Exploration. 4.4. Discussion on Memory Architecture. 4.5. Summary and Status. 5: Memory-Aware Compilation. 5.1. Motivation. 5.2. Memory Timing Extraction for Efficient Access Modes.5.3. Memory Miss Traffic Management. 5.4. Summary. 6: Experiments. 6.1. Experimental Setup. 6.2. Results. 6.3. Summary of Experiments. 7: Conclusions. 7.1. Summary of Contributions. 7.2. Future Directions. Bibliography. References. Index.