This book provides the advanced issues of FPGA design as the underlying theme of the work. In practice, an engineer typically needs to be mentored for several years before these principles are appropriately utilized. The topics that will be discussed in this book are essential to designing FPGA's beyond moderate complexity. The goal of the book is to present practical design techniques that are otherwise only available through mentorship and real-world experience.
Autorentext
Steve Kilts is a cofounder and principal engineer at Spectrum Design Solutions, an engineering consulting firm based out of Minneapolis, Minnesota (www.spectrumdsi.com). Mr. Kilts and his team at Spectrum have successfully completed projects for clients ranging from Fortune 100 companies to small start-ups. His FPGA design experience is extensive and includes applications in audio, DSP, high-speed computing and bus architectures, IC testers, industrial automation and control, embedded microprocessors, PCI, medical system design, commercial aviation, and ASIC prototyping. Mr. Kilts has many years of experience making performance trade-offs for FPGA designs targeting high speed, area reduction, and low power. He holds a master of science degree in electrical engineering from the University of Minnesota.
Klappentext
A practical FPGA reference that's like an on-call mentor for engineers and computer scientists
Addressing advanced issues of FPGA (Field-Programmable Gate Array) design and implementation, Advanced FPGA Design: Architecture, Implementation, and Optimization accelerates the learning process for engineers and computer scientists. With an emphasis on real-world design and a logical, practical approach, it walks readers through specific challenges and significantly reduces the learning curve. Designed to enhance and supplement hands-on experience, this real-world reference includes:
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Waveform diagrams and circuit diagrams illustrating each topic
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Examples that illustrate typical problems in Verilog
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Case studies that demonstrate real-world applications
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Chapter-end summaries that reiterate key points
Ideal for engineers and computer scientists who want to take their FPGA skills to the next level and for use as a hands-on reference, this is also an excellent textbook for senior or graduate-level students in electrical engineering or computer science.
Inhalt
Preface xiii
Acknowledgments xv
1. Architecting Speed 1
1.1 High Throughput 2
1.2 Low Latency 4
1.3 Timing 6
1.3.1 Add Register Layers 6
1.3.2 Parallel Structures 8
1.3.3 Flatten Logic Structures 10
1.3.4 Register Balancing 12
1.3.5 Reorder Paths 14
1.4 Summary of Key Points 16
2. Architecting Area 17
2.1 Rolling Up the Pipeline 18
2.2 Control-Based Logic Reuse 20
2.3 Resource Sharing 23
2.4 Impact of Reset on Area 25
2.4.1 Resources Without Reset 25
2.4.2 Resources Without Set 26
2.4.3 Resources Without Asynchronous Reset 27
2.4.4 Resetting RAM 29
2.4.5 Utilizing Set/Reset Flip-Flop Pins 31
2.5 Summary of Key Points 34
3. Architecting Power 37
3.1 Clock Control 38
3.1.1 Clock Skew 39
3.1.2 Managing Skew 40
3.2 Input Control 42
3.3 Reducing the Voltage Supply 44
3.4 Dual-Edge Triggered Flip-Flops 44
3.5 Modifying Terminations 45
3.6 Summary of Key Points 46
4. Example Design: The Advanced Encryption Standard 47
4.1 AES Architectures 47
4.1.1 One Stage for Sub-bytes 51
4.1.2 Zero Stages for Shift Rows 51
4.1.3 Two Pipeline Stages for Mix-Column 52
4.1.4 One Stage for Add Round Key 52
4.1.5 Compact Architecture 53
4.1.6 Partially Pipelined Architecture 57
4.1.7 Fully Pipelined Architecture 60
4.2 Performance Versus Area 66
4.3 Other Optimizations 67
5. High-Level Design 69
5.1 Abstract Design Techniques 69
5.2 Graphical State Machines 70
5.3 DSP Design 75
5.4 Software/Hardware Codesign 80
5.5 Summary of Key Points 81
6. Clock Domains 83
6.1 Crossing Clock Domains 84
6.1.1 Metastability 86
6.1.2 Solution 1: Phase Control 88
6.1.3 Solution 2: Double Flopping 89
6.1.4 Solution 3: FIFO Structure 92
6.1.5 Partitioning Synchronizer Blocks 97
6.2 Gated Clocks in ASIC Prototypes 97
6.2.1 Clocks Module 98
6.2.2 Gating Removal 99
6.3 Summary of Key Points 100
7. Example Design: I2S Versus SPDIF 101
7.1 I2S 101
7.1.1 Protocol 102
7.1.2 Hardware Architecture 102
7.1.3 Analysis 105
7.2 SPDIF 107
7.2.1 Protocol 107
7.2.2 Hardware Architecture 108
7.2.3 Analysis 114
8. Implementing Math Functions 117
8.1 Hardware Division 117
8.1.1 Multiply and Shift 118
8.1.2 Iterative Division 119
8.1.3 The Goldschmidt Method 120
8.2 Taylor and Maclaurin Series Expansion 122
8.3 The CORDIC Algorithm 124
8.4 Summary of Key Points 126
9. Example Design: Floating-Point Unit 127
9.1 Floating-Point Formats 127
9.2 Pipelined Architecture 128
9.2.1 Verilog Implementation 131
9.2.2 Resources and Performance 137
10. Reset Circuits 139
10.1 Asynchronous Versus Synchronous 140
10.1.1 Problems with Fully Asynchronous Resets 140
10.1.2 Fully Synchronized Resets 142
10.1.3 Asynchronous Assertion, Synchronous Deassertion 144
10.2 Mixing Reset Types 145
10.2.1 Nonresetable Flip-Flops 145
10.2.2 Internally Generated Resets 146
10.3 Multiple Clock Domains 148
10.4 Summary of Key Points 149
11. Advanced Simulation 151
11.1 Testbench Architecture 152
11.1.1 Testbench Components 152
11.1.2 Testbench Flow 153
11.1.2.1 Main Thread 153
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